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Re: SRFI-77 with more than one flonum representation
Brad Lucier wrote:
> I presume you're talking about '387 style arithmetic with 80-bit
> extended real registers. This architecture has no single-precision or
> double-precision operations at all, all operations act on extended-
> precision (80-bit) values in extended-precision registers; so it has
> *no* "implementation of double precision arithmetic". The '387 is a
> correct implementation of IEEE 754 arithmetic,
I presume you mean IEEE 854 arithmetic.
> > While
> > it is possible to perform IEEE-754 double precision arithmetic
> > correctly on the IA32 architecture by writing every intermediate
> > result to memory,
> This is not sufficient to simulate double x double -> double
> operations---pre- and post-scalings, as well as setting the mantissa
> precision to 53 bits, are necessary to eliminate double rounding and
> to compute possible denormal results correctly. Storing intermediate
> results to memory are sufficient to simulate single x single ->
> single operations.
I was assuming the double precision rounding mode, but forgot
about the problems with denormalized numbers.
Alan Watson wrote:
> > If you choose to argue that implementors should be required
> > to solve this problem for single precision arithmetic, then
> > why aren't you arguing that implementors should be required
> > to solve it for double precision arithmetic on the IA32?
> I did. In the second to last paragraph of my first reply to John Cowan I=20
> asked for both "convert-to-single-precision-and-back-to-flonum" and=20
I apologize for missing that. If I understand you correctly,
you are asking for two operations that would round an arbitrary
inexact real to single or double precision, respectively, with
any underflow or overflow that accompanies the reduction in
dynamic range, and returns the result as an inexact real of
I agree that it would be good to add those operations to SRFI 77.
Did I state their semantics correctly?